This invention relates generally to the field of computer architecture. Typically, computers include an interconnected set of computational modules, each performing a specific task or function. These modules are assembled into a full system by connecting the appropriate wires that lead in and out of each through a bus. The bus allows various computer chips or boards to communicate and exchange data. This standardized approach has allowed system designers to physically arrange components in any manner they require without worrying about the details of interconnections.
However, the bus architecture seriously constrains the efficiency of communication among modules. This is a key limitation in today's quest for faster, more efficient computers. Since buses serialize all communications, they create a bottleneck. To make matters worse, the total capacity of the intercommunication remains roughly constant as the system size and the demand for the exchange of information increases. Moreover, the time taken by each transaction must accommodate the physical length of the bus, a crucial factor that limits the communication bandwidth in all but the shortest buses. These deficiencies reduce the viability of the bus as a basis for communication in modern computer systems.
To increase the efficiency in communication among modules, modern multiprocessor architectures have been designed with various different topologies other than the bus. Such topologies include one-dimensional, two-dimensional and three-dimensional topologies.